Moore's law permits the speed and functionality of data switching at Gigabit speeds to be achieved at the chip level. However, Moores Law does not apply to the interconnect and building scalable switch fabrics at these speeds is at the limit of what is technically feasible. The different chip sets soon to be available have been designed independently of, and in parallel with, the development of the standard. The level of performance of the chip sets themselves and the level of achievable interoperability between the different functional layers of 10 Gigabit Ethernet remains to be demonstrated. The systems integration of a individual data switching chips to yield very high performance switching fabrics is so difficult that many industry observers think that it can only be solved using optical transmission and switching. The merging of the LAN world with the MAN and WAN worlds is a complex one of differing hardware and software standards interlinked with major interoperability issues. The objectives of this project are to address these issues and deliver the know-how that makes the difference between the theory of a standard and the practice upon which products can be developed. The project will

• evaluate prototype chip sets for their functionality and interoperability
• develop architectures for performant switch design
• develop a prototype switch to demonstrate mastery of system integration issues
• use the prototype switch to demonstrate LAN, MAN and WAN functionality and interoperability
• contribute to the ongoing standardisation processes
• study architectures and techniques for higher speed Ethernet technologies
• validate the emerging 10 Gigabit Ethernet in Europe and evaluate its impact

The following milestones represent the key deliverables and measurable points in the project

MS1. The design of the 10 Gigabit Ethernet switches to be produced in the project, together with the specification of the demonstrations to be carried out.

MS2. Production of the 10 Gigabit Ethernet switch HW and SW

MS3. Demonstrations and evaluation of switch to switch communications over LAN, MAN and WAN distances

MS4. The results of studies into the feasibility and design of Ethernet switching at speeds up to 40 Gigabit/s

If the project successfully demonstrates 10 Gigabit Ethernet connections over the WAN, it will have demonstrated a potential reduction in the costs of equipment for connection at this speed by a factor of around 50 (from ?180k to ?3.5k ). The impact of such a steep decline in high speed connection costs cannot be underestimated in the impact it will have on the "Wired Society" in Europe, where high bandwidth costs are slowing the take-up of advanced, bandwidth-intensive, services.

How have we done?

We have completed the evaluation of prototype chip sets for functionality and interoperability. We had to change from the original plan, as Vitesse changed direction and withdrew from further manufacture of the 10G front end chips.

We developed suitable architectures for a high performance switch design. A number of changes were made to the original design – a key one was to put a part of the switching fabric onto each line card.

The prototype switch has been produced to show that we have mastered all the system integration issues. Along the way, we have demonstrated that there were aspects of system design that had been overlooked or not mastered by the component manufacturers themselves.

We have used the prototype switch to demonstrate LAN, MAN and WAN functionality and interoperability. In addition, we have demonstrated the circumstances in which MAN and WAN interoperability can be achieved, and the practical constraints.

We have contributed to the standardisation process – at the start of the project, 10G Ethernet standardisation was not completed. Since that time, we have also contributed to standardisation on various WAN activities. We have not been so successful in getting any standardisation efforts up and running for Ethernet beyond 10G. This has partly been due to an industry downturn, which is beyond our control. Elsewhere, we have taken existing and relevant standards, such as the Advanced TCA chassis specification We have also gone beyond just studies of architecture and techniques for higher speed Ethernet technologies and are currently about to receive first silicon for a 100GHz CDR (Clock Data Recovery) chip. As an aside, we recently discovered that this does not completely work correctly in some commercially available 10G SerDes.

Finally, we set out to validate the emerging 10G Ethernet standard in Europe and evaluate its impact. We have successfully done this, although the potential impact is more likely to be constrained by commercial interests. In simple terms, what have we achieved that is tangible:

1. Production of a 8 port 10G Ethernet switch, with a scalable architecture
2. Demonstration of 10G Ethernet over dark fibre for 525km
3. Demonstration of 10G Ethernet over Sonet half way round world
4. Proof that 10G Ethernet can be sent through Sonet repeaters without being re-framed into Sonet
5. An active 10G backplane tester
6. a 10G WAN-PHY
7. Prototype designs/chips to form part of a 100G Ethernet chipset